Research On Preparation And Doping Methods Of Graphene Field-effect-transistor

Graphene is a new 2D nanomaterial with excellent electrical properties. Theoretically, the intrinsic graphene have carrier mobility as highly as 200000 cm~2/(V×s), which is nearly 200 times of that of silicon. Perfect lattice structure makes that electrons transport almost without scattering in intrinsic graphene, the Fermi velocity is nearly one three-hundredth of light. Excellent properties make graphene has potential applications in many areas, such as sensors, transistors and so on.Based on the traditional wet transfer process, a graphene standard transfer operating procedure was established which was suitable for laboratory and provided effective solutions to graphene damage, backside graphene residuals issues. A PMMA(polymethyl methacrylate) coverage index was established to present the amount of PMMA residual. Experiments were set to study how drying temperature affect PMMA residual on graphene surface. We found that higher baking temperature brings more PMMA residual, besides AFM showed more bad roughness for graphene surface after baking. A Heat-Free-Transfer technology was proposed based on graphene transfer standard operating procedures. Heat-Free-Transfer technology abandons the baking process, adjusts the photoresist removing process and finally high quality graphene were obtained.On the basis of the transfer process we prepared two kinds of graphene MOSFETs. One is a back-gate structure graphene field effect transistor(GFET) which used heavily doped silicon as the back gate electrode. Furthermore, RF GFET with buried gate was prepared, in this RF GFET 80 nm width gate was defined with electron beam lithography, 30 nm HfO2 was used as gate dielectric and Ti/Au electrodes. Electrical tests showed the Dirac point voltage of these two kinds of GFETs is greater than + 30 V which means graphene was P-type doped. S-parameters of the RF GFET were tested and then converted to h-parameters which shows a 1.09 Ghz cutoff frequency and has improved to 4.5Ghz after de-embedding for this device.Silicon nitride deposition process with PECVD equipment was studied and we used simple back-gate structure GFETs as experimental devices. We deposited 25 nm silicon nitride on the surface of GFETs with power 10 W, temperature 200℃, pressure 55 Pa, SiH440sccm/NH340 sccm, N2 150 sccm. According to these arguments the deposition rate can be controlled below 1?/s. Raman spectra showed weak D peak, the position of G peak moved to lower position, electrical test observed Dirac points for GFET has moved left to about-25 V. A 19 days tracking test found that this silicon nitride-doped graphene showed some stability, VDirac tended to be stable and gradually moved to-5V.