Based On The Time-interleaved Sampling Structure Of The High-speed Adc Systems

With rapid development of digital communication technologies, the requirement of analog to digital converter rate is sharply increasing in many applications. Although the speed of single-chip ADC has a remarkable growth these years, the precision of these ultra-high-speed ADCs still needs to improve. The only way can break through the speed bottle-neck caused by today's ADC technologies, is to build a parallel ADC system using time-interleaving technology. Time-interleaving technology is the only method to obtain a ultra-high speed ADC system whose sample rate is multi-times of single ADC chip's sample rate without limitation of input signal.However, because of perfect co-operation needed among the sub-channels, the parallel ADC system by nature has sample errors. There are three main sample errors, one is caused by the mismatch of sub-channel's gain, one is caused by the mismatch of sub-channel's offset, and the other is caused by the mismatch of sub-system's sample clock. These errors will bring distortion to the digitalized data. And the cost will be tremendous if one intend to calibrate these mismatches on hardware side. One of the research emphases in this paper is to calibrate these errors in software.A four-channel ultra-high speed ADC system based on time-interleaving technology is introduced in this paper. This ADC system realized the time-interleaving technology in digital ways, so the system is flexible. The maximal sample rate of this system is up to 1GSPS, and the precision is 8-bits. The author uses a PLL and clock distribution chip to generate the sample clock needed by the ADC chips. And use FPGA+DSP to analyze the digitalized data and do the calibrate jobs. After the calibration, the system's ENOB can beyond 6.5 bits.In this project, the author designed and debugged the hardware platform. Analyzed the data digitalized data on both time and frequency domain. Studied the calibration algorithm on Matlab and finally realized it on the DSP. In the end, the author did some evaluation on this system.