Design And Implementation Of 2D-to-3D Image Conversion And Compression System Based On FPGA

The three-dimensional (3D) technology makes it more realistic to show real-world.3D display technology brings us to a new virtual world which is full of bizarre and beauty, especially in medicine, film and television entertainment.3D display technology has become part of people’s lives. However, the production of 3D resources is both time costs and expensive, especially in the entertainment. So how to take full advantage of existing 2D resources to less the cost of producing 3D resources is currently a hot research. There are two ways to generate 3D resources from 2D resources.The one uses multiple cameras to capture multiple images or single camera to shoot moving scene, this method uses multi-purpose depth information. The other uses single still image, it uses monocular depth information.This thesis uses single image to generate relative depth information based on contour extraction. Combining DIBR three-dimensional display technology, this thesis achieves 2D-3D conversion. The difficulties of 2D-3D image conversion and compression system are:how to extract depth map from two-dimensional image, how to render 3D image using depth map and original image, how to store the image effectivly. In generating depth map part, this thesis uses coutour imformation of scenes to estimate depth map.This method is efficient and easy. In 3D displaying part, this thesis uses DIBR technology after compared with other techonology. This thesis can get better 3D just using a red-blue glasses and a common screen. What is more, this thesis uses JPEG standard to store the 3D image.This thesis uses Xilinx Zedboard platform to impliment the 2D-3D image conversion and compression system. Taking advantage of the hardware and software collaborative feature of Zedboard platform, at PS part this thesis impliments software controller based on Linux operating system, Opencv and Qt library, at PL part this thesis impliments IP cores of each algorithm module based on FPGA. These IP cores are software called in the system.