A Validation Method Based On 1394 Bus Monitoring System Verilog Logic

Bus Monitor,as the name implies, is to monitor the communication data. It is an important part of the fault simulation system, the integrity of its function, reliability of the work of the development of high efficiency, and also play a positive role in improving the efficiency of the simulation system development and shorten the development period of the system. The reliability and effectiveness of the Bus Monitor laid the important position in to verify the system functions. In order to locate the state of the system, fault analysis and so on, in this paper, the design of bus monitor function module, and put forward a kind of effective method validation.IEEE 1394 bus monitor protocol has been introduced in this paper, and also introduced the external interface signals of the bus monitor functional logic. Through the discussion of shortcomings of the traditional verification method, finally, I adopt the System Verilog to build a hierarchical object-oriented validation because of its highly efficient method. Contract awarding mechanism by random incentives to functional verification of Design Under Test, completing validation function modules of the bus monitor fully.Firstly,I have introduced IEEE1394 protocol and analyzed its structure, based on this, the validation of the object of the overall architecture is introduced in this paper. Through mastery of overall architecture, we can understand the object under test, namely the bus monitor function modules, including a detailed description of its function and components. Can only be further understanding of design enough to verify its function. To verify the bus monitoring function, we must to understand the structure of the platform and the platform of verification, ultimately choose to build hierarchical SystemVerilog verification platform. SystemVerilog platform compared to traditional authentication platform in characteristics, respectively from the aspects of language, structure, function is introduced in detail. According to its functional design requirements,to set up un unique verification platform in bus monitoring function module, and integrity test was carried out on the platform. All of these are in order to validation the features of the design better, how to carry out the purpose of the test and test is the focus, through classifing resources of the test,to achieve the goal of verify the needs in this article.The virtual simulation, makes the bus monitor function adequately complete verification, and the validation results indicates that the monitoring functions conform to the requirements of the function of the bus. The functional verifying of the bus monitor, can improve the efficiency of fault handling in simulation system and the of recording ability in the real-time state.