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Establishment And Verification Of Cross-point Array Unit For 1S1R Verilog-A Model

Posted on:2021-01-06Degree:MasterType:Thesis
Country:ChinaCandidate:M QiFull Text:PDF
GTID:2428330629480310Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
With the increase of the scale of integrated circuit,memory,as an important part of integrated circuit,has more strict requirements on storag,e capacity,read-write speed and power consumption.The optimization of memory becomes more and more important.The traditional flash memory has gradually failed to meet the requirements.Non-volatile memory has become an excellent substitute for memory.RRAM is one of non-volatile memory.However,under the requirements of high integration,crosstalk and leakage current are easily generated between RRAM arrays.To solve this problem,the 1S1R structure is proposed based on RRAM,which is composed of a strobe and a memory in series,can effectively avoid crosstalk and leakage current,so as to improve the integration degree.Therefore,1S1R circuit model has become more and more concerned.In this paper,a compact model of one threshold switch selector?1S?and one bipolar resistor RAM?1R?for circuit simulation is proposed.Firstly,the bistability of the selector is taken into account and the mathematical formulas describing the two different states before and after threshold switching are given,and the selector compact model is established by Verilog-A language.Secondly,the parameters(Vth1,Vth2,Vop,?,?,Rs)in the S model are adjusted to match R,especially Vth1 and Vth2 can be adjusted according to the set and reset voltage of R.Then,the Verilog-A model of 1S1R is built,and the circuit unit of 1S1R is tested by several different waveforms including triangle wave,sine wave and rectangle wave to test its adaptability in different working environment.After the unit test of 1S1R is completed,the 1S1R unit is applied in the 7T1R circuit,and the R in the original circuit is replaced by 1S1R.It is found that the current in the closed state and the power consumption is reduced on the basis of keeping the original function unchanged.After that,cross point array is built with 1S1R cells,and the cells in the array are controlled from the horizontal and vertical directions respectively by decoder to gradually verify the crosstalk and power consumption problems in the array.Because of the high non-linear selector,the off state current of RRAM is significantly reduced,the power consumption of the new 1S1R structure is lower on the cells,the reading window is larger,and the crosstalk problem is avoided in the array.Finally,it is concluded that the crosstalk and power consumption of RRAM are effectively solved by adopting the new 1S1R structure.
Keywords/Search Tags:RRAM, Selector, Verilog-A, Simulation, I-V characteristic
PDF Full Text Request
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