Software-Hardware Co-design And Verification Based On IEEE1394 SoC

With the development of science, the requirements of data transport speed and reliability are getting higher. IEEE1394 protocol is a high speed, reliable and low cost serial bus. It can be used as peripheral bus, standby bus of backboard parallel bus, or local area network bus. As IEEE1394 has characters such as high transport speed, long transmission distance, supporting hot plug-in and plug-out, it has been used in areas such as multimedia and mass storage. Meanwhile, complex IC system designed with So C has characters of small volume, low-power consumption and light weight. Design complex IC with So C can improve system performance and increase system modules’ reusability.Based on IEEE1394 protocol, this paper analyze IEEE1394 So C system architecture, integrate resources of micro CPU, storage device and I/O interface on one chip, illustrate the composite of system modules. By analyze of complex So C system, put forward the method of IEEE1394 So Chardware-software co-design, and illustrate hardware-software co-design flow.In the process of IEEE1394 So C verification, bring in UVM methodology to improve verification efficiency. In consideration of factors, such as complexity, the necessary of verification and sufficiency of simulating So C environment, this paper choose to implement system design and verification by hardware-software co-design. Construct IEEE1394 So C virtual verification environment using SV language, design corresponding plan and requirements. Illustrate So C’ module-level and system-level verification, implement system-level verification using hardware-software co-design, prepare hundreds test programs, and exemplify 3 typical verification case. In conclusion of verification results, design of IEEE1394 So C in this paper has achieved function requirements specified in 1394 protocol.After the process of system-level virtual prototype verification, a FPGA prototype verification Solution is put forward to verify hardware design directly and roundly. Illustrate FPGA verification platform, and exemplify a verification of data transport reliability between two nodes.