Research On Reusable Verification Platform Based On UVM

With the development of integrated circuits process and design technology, the So C design scales down and is becoming increasingly complex. This causes the verification of So C design being more and more difficult, which has became a serious challenge in integrated circuits design. In this thesis the characteristics and requirements for So C/IP verification were investigated based on System Verilog verification language and universal verification methodology(UVM). In combination with the IP module level in So C design, the verification platform and associated universal verification components(UVCs) were also designed according to the protocol specifications. In addition, some key issues of the verification method and UVCs were discussed; for example, how to reuse the verification platform in other IP modules and system level modules.In the design stage of verification platform,the system framework and verification requirements for So C/IP was analyzed, and then the form combining bus interface model and abstract hierarchical structure was adopted based on UVM, laying a foundation for the realization So C/IP verification platform in the next stage. In order to ensure the reusability of verification platform, the UART and APB UVCs were abstract designed, and the top control module environment nested the UVCs sub-environment. The achieved verification platform was random and controllable by adding random constraint, transaction, and phase mechanism into the low-level components. In the implementation stage of verification platform, the covering points were decomposed and random transaction level incentive was used to compile test case with UART design module. The code coverage rate and function coverage rate reached 99.60% and 100%, respectively, with only one test case going through. The test efficiency was improved. Meanwhile,, VCS automatically generated a report after simulating, which record the verification components running in verification environment, register configuration information, and the right or wrong information of transmission through UVM_INFO.SPI module was selected to study the reusability of the verification platform on module level by using the same platform and user-defined UART and APB UVCs. The SPI verification environment was automatically generated by top environment. The simulation of test case showed a code coverage rate of 100%, indicating the reusability of this verification platform on module level. In order to validate the reusability on system level, APB sub-system was adopted. Structure diagram was used to illustrate the UVCs structure and the division of environment when this verification platform was applied to APB sub-system. Above all, the reusable verification platform based on UVM is superior to the traditional one in the aspect of random, reusability, and automatization, and is feasible for verifying integrated So C.