SCU Chip-Level Verification Based On VMM

Verification stays in very important position during integrated circuit development process. Resources such as human resources and time expense, server CPU, harddisk and EDA software license usage during verification reach up to 70% or more of the whole project cost in SOC development based on IP reusage. Requirements from customers drive the chip to be more and more complex and support more and more functions, and multi CPUs, DSPs, VPU and GPU, and many communication interfaces are integrated into the whole chip while marketplace ask new products release cycle to be much shorter, which will shorten SOC research and development cycle, however function and performance requirements are not degraded correspondingly. the solution to solve this contradiction is to ask engineers to work with higher efficiency, it is to use higher efficiency verification tools and methodology. This is an commercial developing project, and is to realize chip level verification of SCU of one analog baseband chip used on smart mobile phone platform under VMM developed verification environment.It is to research advanced and high efficient VMM verification methodology first. this part is to research verification structure, characteristic and complete verification flow of VMM. then it is to analyze verification requirements, system architecture of verification object, various control function, and verification scenario deeply, which will be only reference for designing verification points at next step. this part is to analyze location, functions of different modules and hand-shake between modules mounted on AHB at top level of verification object, especially SCU verification scenarios covered by verification points are emphasized. after that, design and implementation of verification points based on real verification scenarios, it is to develop testcases to cover all verification points. this part is to develop common structure of testcase realization based on specialty of verification object, and tetscase to cover some specific verification points can be cut flexibly and finally to cover all verification points. in the end, to analyze various issues met in verification process and work out solution. this part is to dig out root cause of various environment issues, code issues occurred during debug and work out valid solutions.Chip level functional verification based on VMM lives up to target and expectation with good performance from real verification results. under the premise of ensuring good verification quality, it saves verification time and resources, and speeds up product pace to market.comparing to previous projects, verification burden is almost double with nearly the same human resources in current project, verification time reduced from six months to four and an half months, and to enhance verification efficiency at least 30%. all these results show that VMM was a good theoretical and practical guideline for chip verification.