Research And Implementation On The Key Techniques Of Microprocessor I/O System Reliability Design

With the rapid development of integration desity and manufacture process of semiconduct, microprocessors face more serious threatens of soft errors. In response to these challenges, the industry companys focus on developing new fault tolerance design techniques to increase the reliability of microprocessors.Modern microprossors develop towards multi cores and SoC(System on chip). Different from traditional microprocessors which are only composed of core and memory system, modern microprocessors usually integrate I/O system on chip. Traditional microprocessor reliability design, which mainly focuses on core and memory system, pays little attention on I/O system. With the higher soft error rate of semiconduct device, the I/O system in microprocessors has be hardened.Because the I/O system in microprocessors has different structure and function from core and memory system, its reliability design must be based on its own features. This thesis presents some key techniques on microprocessor I/O system reliability design. The main works and innovations of this thesis include:(1) Design and implementation of RTL code auto generation tool for various bit width ECC code and decode. There are many data pathes with various bit width in I/O system. If all these data pathes are proctected by ECC code, the designers have to learn the complexity ECC algorithm and design the code and decode modules, which is a long and difficult process. By using the tool presented in this thesis, the ECC code and decode module can be automatically generated by indicating the module name and bit width. This tool makes the reliability design much easier and accelerates the design process.(2) Design and implementation a high reliable asynchronous FIFO based on two-dimensional parity. The I/O system usually contains many clock domains. The asynchronous FIFO is used to transmit data acrosing different clock domain. With the development of I/O system in microprocessor, the asynchronous FIFO becomes wider and deeper. So these asynchronous FIFO has to be hardened to increase the I/O system reliability design. Traditional asynchronous FIFO reliability design usually use parity or ECC code. The former can only check odd bit error, while the latter has a great impact on performance because of its complexity algorithm. This thesis demonstrated a new reliable FIFO structure by using two-dimensional parity, which can check and even correct errors and brings only a little performce loss.(3) Design and impementaion of high reliable IOTTE cache. In modern microprocessors, the I/O system contains not only a data path for I/O data, but also some complex structures, such as caches. To implement I/O virtulazation, modern microprocessor uses IOMMU(I/O Mapping Management Unit) for translate between virtual address and physical address. IOMMU ususlly use IOTTE cache to cache the TTE(Traslation Table Entries), so that the translation flow can be accelerated. This thesis presented a reliable IOTTE cache with various harden techniques. This cache can tolerance soft error and increase the reliability of microprossors.In summary, this thesis presents the researches on some key techniques of microprocessor I/O system reliability design, demonstrates the design and implement of some high relibile modules which has been used in engineering practice. This can effectively improve the reliability of the I/O system in microprocessor and reduce the design complexity. The works of this thesis has a positive meaning in microprocessor I/O system reliability design.