Leveraging mixed process three-dimensional die stacking technology for cache hierarchies and reliability

Aggressive technology scaling has led to smaller transistor sizes and steadily improved transistor performance. However, on-chip global wires have not scaled at the same rate causing interconnects to emerge as one of the key bottlenecks. This has an especially pronounced effect on future cache hierarchy design where interconnects exchange data between numerous cores and caches. In addition to rendering processors communication-bound, technology scaling has also decreased processor reliability. Shrinking transistor sizes and lower supply voltages have increased the vulnerability of computer systems towards soft errors (also known as transient faults).;In the first part of this thesis, we propose a reliable processor architecture that uses an in-order checker processor optimized to reduce the power/performance overheads of redundancy. We then leverage the "snap-on" functionality provided by 3D integration and propose implementing this redundant checker processor on a second die. This allows manufacturers to easily create a family of reliable processors without significantly impacting the cost or performance for customers that care less about reliability. Most importantly, we advocate the use of an older process technology for implementing the checker die that is more error-resilient, showcasing the advantage of mixed-process 3D integration. In the second part of this thesis, we propose the design of a reconfigurable heterogeneous SRAM-DRAM cache. By stacking a DRAM die on top of a SRAM die, the SRAM cache can grow vertically by enabling the DRAM bank above based on the application's working set requirement. This artifact would not have been possible without exploiting mixed-process 3D integration. Such a heterogenous cache design allows us to reap the benefits of DRAM's density and SRAM's superior power and delay characteristics.;Emerging three-dimensional (3D) integration technology enables vertical stacking of silicon dies, yielding high density and low latency interconnects. This results in increased processor performance as well as reduced power consumption because of shorter on-chip wires. Another salient advantage of 3D stacking is the ability to stack heterogeneous dies that have been fabricated in disparate process technologies. This dissertation explores novel applications for 3D die stacking at the micro-architecture level with an emphasis on this mixed-process integration. We find that reliability and cache-hierarchy design can benefit from 3D die stacking and we explore the various solutions that call help mitigate these challenges in future processor design.