The Research For Low Power SRAM Design Methodology

SRAM(Static Random Access Memory)is one of the important components in electronic system.It is applied to store data and instruction temporarily.Because of high-speed,low-power and easy to be integrated,it becomes the primary candidate for cache in CPU.In the modern high performance CPUs,the area of SRAM is over 80%.By the booming market of mobile internet,wearable electronic devices and internet of things,the power consumption of chips will be facing the strict requirement and serious challenge in the next a few years,so the low power design methodology for SRAM is becoming more and more important.The main contribution of this thesis is to explore the low power design methodology for SRAMs,which is focus on schematic level,can be used with the scale-down of technology and will not affect the performance too much.In this thesis,we propose a new charge-recycling SRAM,bit-line charge pump SRAM and voltage supply charge pump SRAM techniques.First,we introduce the principle,classify and development history of SRAMs.Second,we analyze the circuit structure,optimizing mothod and estimation of stability,then analyze the total power consumption of conventional 6T-SRAM,and find out bitline charging and discharging activity is the most significant part among various power consumption components in SRAMs.Furthermore,the bitline power consumption in write cycle is more than that in read cycle.So the key point of the thesis is focus on bitline charging and discharging activity in the write cycle.Thrid,for bitline charging and discharging power consumption,the existing charge-recycling technique can reduce a lot of bitline power consumption,however,there are some shortcomings such as the high complexity and additional circuits are required.In this thesis,we propose a new bit-line charge-recycling solution to improve the inherent drawbacks of existing method.In addition,hierachical bitline scheme is presented in read cycle and two types of 8T-SRAM cells are adopt in the same array.These three improvements reduce the power consumption and enhance the stability.Fourth,the existing charge pump SRAM has some shortcomings,such as different performance for two splitted arrays,decreasing stability,high complexity and requiring additional DC voltage supply,et al.The proposed bit-line charge pump SRAM conquers these shortcomings.Furthermore,another voltage supply charge pump SRAM circuit is proposed.The key point of charge pump SRAM technique is,sharing the bit-line charge in write operation,and then re-using the charge by the function of charge pump.Last,post simulation is applied to prove that all of the proposed techniques can be manufactured and to analyze and compare.A 64 Kb 8T-SRAM layout is completed with 65 nm ultra-low-power technology.The proposed new bitline charge-recycling solution,hierachical read bitline scheme and two types of 8T-SRAM cells are applied in this SRAM design.The power consumption is 36.9% less and Static Noise Margin is 162% more than conventional 6T-SRAM in the same technology.An 8Kb bit-line charge pump SRAM layout is designed with 180 nm CMOS digital technology.11% power cost is saved comparing to conventional 6T-SRAM without charge pump.This proposed bit-line charge pump SRAM is embedded into an 8051 MCU,and the system runs smoothly and fulfills the specification.A 32 Kb voltage supply charge pump SRAM layout is completed with 130 nm RF technology.The simulation result indicates that it reduces 16.2% power consumption compaired with conventional 6T-SRAM and increases 80% highest frequence compaired with bit-line charge pump SRAM in the same technology.