Font Size: a A A

The Aging Test Research On The High K Metal Gate CMOS

Posted on:2015-03-11Degree:MasterType:Thesis
Country:ChinaCandidate:K JiaFull Text:PDF
GTID:2308330473955785Subject:Integrated circuit engineering
Abstract/Summary:PDF Full Text Request
Aging test is a most effective reliablity testing for initial failure analysis. With the semiconductor technology continues improvement and then chip threshold becomes more low and increasing integration. Module development of automatic test equipment can meet chip testing requirements. Based on GB/ OS, these different chip characteristics need different test scenarios. Therefore, the principle is the same, but the detail process is different. For the advanced chip technology, the existing external aging test scheme has met the greates challenge already. Not only to control the test cost, but also greatly improve the equipment detection capability in High volun manufactring condition. How to effectively integrate chip terting becomes a hot topic in the industry.This paper keeps the focus on 32 nm High K metal gate CMOS chipset aginig test model, method design and achievement:1. For the test model, through the experimental data, showing how to judge the reliability of aging test results and statistic method. At the same time, the author also specially introduces the monitoring model of the equipment itself. So in order to make reliable test result, first of all, the owner must ensure the reliability of the test equipment.2. For the hardware solution plan, according to method requirement and 32 nm CMOS characteristics, modify the haredware, especially for temperature control.3. For the sofetware solution plan, because of the restrictions, the article could not show the actual testing procedures, but can describe the analysis of the test logic structure, aging test program from self audit and Burn In test program, logical relationship of the test demonstrated according experimental records.4. For the failure common analysis introduction, analyze the example; show the method of failure analysis and the accelerated aging test exposure of the common failure factor.At the same time, compare with 22 nm and 32 nm chipset characteristics, though the discreption between hardware, software and failure analysis, then shows 22 nm aging method. At last, prospect new aging test method for next generation products.
Keywords/Search Tags:Reliability Test, Aging Test, 32nm SOC, Failure analysis
PDF Full Text Request
Related items