The Design Of 2 Ports EHCI And Its Embedded API

EHCI(Enhanced Host Controller) is the international standard host interface of the USB(Universal Serial Bus) version 2.0, and it has been widely used in the world.There are three main purposes of this study, first is to design a version of faster host controller by using the hardware design language of Verilog, and the transmission speed should be infinitely close to the theoretical value of 480Mb/s of EHCI, additionally the RTL code must be synthesized; second is to achieve two-ports interface which has been supported by EHCI specification; third, add additional registers in the design and design API(Application Programming Interface) interface based on the C language. By using the API, EHCI can work without the standard EHCI driver in the system.The first step of this study is planning design architecture, in this paper it describes how to calculate those important argument of design systematically, such as FIFO size, pipe-line depth, etc. After those argument has been determined, the second step is planning the function of each module, such as clock domain selection, how to coordinate the work between those modules, as well as cross-clock-domain issues. The third step is to achieve RTL code based on the previous plan, the RTL coding must follow the code style strictly to ensure that the code can be synthesized into net-list table. The forth step is simulation, the simulation environment is achieved by using the UVM(Universal Verification Methodology)verification methodology, which is comprehensive and high efficiency. When the simulation is coming to the end, it begin to do FPGA test and also verify API interface code on the FPGA. The final step is to test EHCI transmission speed in the simulation environment, and also do synthesize for the RTL code to get the area information of the EHCI.Through this design it confirms that the fastest transmission speed of the new designed EHCI can reach 416Mb/s, which has been relatively close to the theoretical value of 480Mb/s, in fact the fastest speed of the EHCI on the market is on the 300Mb/s or so. In order to achieve the fastest transmission speed, it requires two preconditions, the first one, driver should not plan the useless transmit control packets into the traversal list, and the amount of each transfer packet size should be or close the maximum packet size. The other one is the transmission speed of the device connected on EHCI should be fast enough. The effect brought by the speed increasing is about the increase in the area, in the view of the results obtained by synthesis, the area is double compared with the previous version of EHCI. It assumes that the EHCI in the market is in a more reasonable balance point between speed and area’s trade-off, this design has put aside this balance and pursued the speed, the result is that the speed is 30 percent faster, the area increased by 100 %.