Research On The Design Of Embedded SDRAM Controller

Nowadays , as the technology of communication and multimedia developing fast , the demand for mass storage products and high performance is becoming even more urgent . Modem processor performace increase at the rate of 60% per year , while the bandwidth of a DRAM chip increase by only 15%~20% per year , with latency improved by only 7%.Therefore Computer systems are becoming increasingly limited by memory performance .Because Synchronous Dynamic Random Access Memory(SDRAM) has the advantages of mass storage , high speed , burst read/write and low cost , which is widely used in various fields . The control of SDRAM is relatively complicated , so we need to design the SDRAM Controller .In this paper , a design program of SDRAM Controller shared by the variety of resource have been put forward by studying the basic operation of SDRAM memory and functions of traditional SDRAM controller , it studies the functions of top-level module first, and classifies these functions then distributes them into different submodules, and then completes each submodule from the bottom up , Specific designs the utomatically refresh , read and write , arbitration functional module , etc . and at last , connect the submodules to each other , the top module is formed .A detailed description of the controller have been done from the overall structure of the idea to the specific logic design in this paper . and it realizes all kinds of basic operations of the controller , such as initialization, auto-refresh, auto-refresh read&write operation , priority arbitration , and so on . Use the verilog language to describe it and demonstrate that the controller functions and sequential logic is correct..