Research On Key Techniques Of Radio Resource Allocation In Relay-enhanced Cellular Networks

Today,with the rapid development of computer technology, digital systems have get more and more applications in people’s lives. The performance of digital systems,largely dependents on the front end of the Analog-to-Digital Converter now. A high-performance Analog-to-Digital Converter is the premise of obtaining a high-speed and high-performance digital systems. however,The limitation of traditional production process of Analog-to-Digital Converter makes the requirements for high-speed and high-performance can not be met. Therefore, the Time-interleaved Analog To Digital Converter(TIADC) become the inevitable choice. Because of the error, offset and sampling clock of system caused by the different sub-ADCs have reduced the sampling performance of TIADC system, how to improve system performance of the TIADC system has become the key of research. Industry and academia have proposed a variety of research methods about the study of the error correction systems of the TIADC, and the digital calibration technique is one of the feasible approaches among the these methods.First, this paper analyzes the sources of error of TIADC, elaborates effectively the principles of producing error, and more specifically analyzes the error of bias, offset and the sampling clock of the TIADC system in frequency-domain. Hence get the appropriate error correction algorithm based on the principle. The performance parameters of SFDR of the system which we obtained through MATLAB simulation results verifies the feasibility of the algorithm and this makes the system performance of TIADC after calibration be greatly improved.Secondly, in the first place we estimate the TIADC error in the DSP and the error estimates implementation of the algorithm, then adjust the error through the ADC auto-calibration function. In order to get the generality of algorithm of calibration, we studied and implemented error of calibration algorithm based on Lagrange polynomial interpolation. We evaluate the performance of the system through the calibration performance of the ADC’s Spurious Free Dynamic Range(SFDR) dynamic performance parameters.Finally, achieve the circuit design of the TIADC error correction with a dual-channel 8-bit and 1GHz in FPGA. It obtained the the possibility of the error correction algorithm by the comparison of the data before and after calibration. Theexperimental results show that the designed circuit use less hardware resources and get better performance.