Modeling And Mechanism Researching Of ESD Protection Circuit Of CMOS Digital Circuits

In recent years, disturbance and damage of digital circuit caused by HPM and the protection technology for these have become the focus of attention of many scholars. To further analyze the interference process and damage mechanism of digital circuits affected by microwave, it is necessary to study device-level effects of digital circuits.CMOS technology in digital circuitry applications still dominate in the current. On the other hand, The microwave pulses which coupled into the circuits will act on the ESD protection circuit firstly, since the ESD protection circuit is widely present in both the input and the output of CMOS circuits and relatively independent of buffer circuits and core logic devices. Although some scholars have developed HPM effects and modeling work about the unit device- the inverter in CMOS circuits including ESD circuits, but the relevant part of the ESD model does not consider the parasitic parameters which plays a key role in ESD pulse energy discharge channel. In this paper, CMOS inverter as the starting point, focus on SPICE modeling based on HPM effects of MOS transistor in ESD protection circuit, we build a more complete HPM effects typical CMOS inverter circuit model combined with previous works about mechanism researching of HPM effects of digital circuits on the lab and a microwave pulse injection simulation is did. Thereby, a number of HPM effect mechanism rules are analyzed.First of all, the parameters of parasitic MOS transistor and substrate resistance circuit have been optimized, ESD protection circuit(ggNMOS and gcPMOS) equivalent model has been constructed, and single-tube function circuit has been verified through simulation, these are based on the principles of ESD protection circuit of CMOS digital circuits port. Secondly, the HBM simulation test circuit is established and the circuit uses a single-stage inverter as the load. The ESD protection circuit, which is composed of ggNMOS and gcPMOS in the circuit port, function tests show that ESD protection circuit model constructed in this paper can effectively reduce the inverter input level below the sensitive voltage range and the port discharge waveform simulation results obtained good agreement with the literature when the input is HBM model test waveform. Finally, simulation study of a multi-level inverter HPM circuit model(the ESD protection circuit located at the input port adopting the above-mentioned circuit topology) is conducted by the HSPICE software and the microwave pulse injection method. Results compared with the simulation results of no ESD protection circuit. Understanding and knowledge of the working mechanism of ESD protection circuit in the CMOS digital circuits destabilizing effects of HPM through the above works.The calculation and simulation results show that: Input port ESD protection circuit has a certain capacitance loading filtering effect, which increases the disrupt threshold. At low frequency microwave pulses, the ggNMOS and gcPMOS of ESD protection circuit response to dynamic equilibrium, making the CMOS inverter input logic disrupt level reaches a steady state to slightly below VCC/2. At high frequency microwave pulses, the ggNMOS and gcPMOS of ESD protection circuit response equilibrium is disturbed, leading to the steady point of CMOS inverter input logic disrupt level continues to increase with the frequency of the microwave pulse rising. The minority carrier high frequency response differences of gcPMOS and ggNMOS is the main mechanism of these effects.