Simulation And Optimization Of FD SOI CMOS Devices At High Temperatures

Silicon-On-Insulator (SOI) CMOS Circuits has been widely used in the field of low-power and high performance IC owing to its advantages in low junction-capacitance, reduced second order effects, and latch-up immunity. However, since the buried oxide layer is also a thermal insulator, the power consumed in the active device region can not be dissipated easily. Therefore, self-heating effects on SOI circuit performance are of concern. Thus, particular attention is paid on model construction, characteristics analysis and parameter optimization for their high temperature applications.Based on Fully-Depleted SOI technology, a quasi-two-dimensional CMOS inverter comprising a MOSFET and a PMOSFET of channel length 0.18μm is establish. By the employing of ISE TCAD, some adjustments have been made to the models. The transport models of simulation are based on Hydrodynamic and Thermodynamic models. Furthermore, Density Gradient quantization model is also considered for the sake of exactly computing effective mobility and impact ionization generation rates as a function of temperature. Band gap narrowing effect and short-channel associated Drain-Induced-Barrier-Lowering (DIBL) effect are also taken into accounts. Mixed mode simulations have been carried out in order to predict and investigate temperature and self-heating effect over a temperature range of 300K~600K. As a result of simulations, both static and transient electrical characteristics of the inverter and MOSFET are obtained. The simulated results indicate that, the threshold voltages of both NMOSFET and PMOSFET are sensitive to temperature. Furthermore, a negative output conductance and significant reduction in drain current are exhibited as the increase of device temperature. Besides, a significant rise of leakage current can be observed. In addition,the high-low voltage level switch region broadens and noise margin declines when the temperature raises. Withal, the transient simulations reveal how speed and power depend on ambient temperature. Therefore, some optimizations have been performed to the traditional SOI circuits. The study confirms that self-heating effects can be overcome by making a cut box in the buried oxide layer. The optimum length of cut box is equal to gate length and the best cut position is under gate. But there are also some limitations to this DSOI structure in its high frequency applications because of its speed performance losing. Thereby, a new device structure called AlN-DSOI is proposed. In comparison to other two structures, the improved structure has better electrical and driving performance on the basis of releasing the floating body effects and thermal transfer problem in SOI circuit.