Research And Implementation Of Hardware-efficient Parallel Structures For FIR Digital Filter Based On Iterated Short Convolution Algorithm

The finite-impulse response(FIR) filter has been applied in many digital signal processing(DSP) systems. In some applications, such as video processing and 4G communication, the FIR filter must have a high throughput, while in other applications, such as mobile phone and handheld terminal medical equipment, the FIR filter’s power must be low. Parallel processing not only can be used to increase the sample speed but also can be used to reduce the power consumption of a FIR filter. But the hardware implementation of the parallel FIR filter increases linearly with the level of parallelism. Therefore, it is very meaningful to reduce the complexity of the parallel FIR filter.Firstly, this paper reviews recent research trends in parallel FIR filter in China and other countries, discusses the advantages and disadvantages of the existing methods.Then, Based on fast convolution algorithm, improved parallel FIR filter structures are proposed for linear-phase FIR filters. The proposed parallel FIR structures not only use fast convolution algorithm to reduce the number of sub-filters, but also exploit the symmetric coefficients of linear-phase FIR filter to reduce half the number of multiplications in sub-filter section at the expense of additional adders in pre-processing and post-processing blocks. The proposed parallel FIR structures save a large amount of hardware cost for symmetric coefficients from the reported parallel FIR filter structures, especially when the length of the filter is large. Specifically, for a 4-parallel 144-tap filter, the proposed structure saves 36 multipliers(14.3%) from the ISCA structure, with the overhead of additional 11 adders. The proposed structure saves 36 multipliers(14.3%), 23 adders(6.6%), and 35 delay elements(11.0%) from the improved FFA structure. Based on the same idea, improved polyphase decimation filter structures are proposed. The improved structure saves half of multipliers from the traditional structure.Finally, the proposed structures and the existing structures are implemented in Verilog HDL based on FPGA.