Design And Implementation Of Parallel FIR Filter Based On FPGA

The linear phase FIR(Finite Impulse Response)filter is a stabe system,which widely used in various signal processing fields,such as communication systems,aerospace systems,radar systems,and so on.With the development of electronic information technology,the operating frequency requirements of the FIR filter have exceeded 1 GHz or higher in these fields.Parallel technology can improve the operating frequency of the filter in multiples,but its hardware resource usage will also increase exponentially,which greatly limits the practical application of the parallel filter.In this study,a parallel FIR filter has been designed based on FPGA,and the specific scheme has been given based on the FPGA hardware characteristics and sub-filter coefficient characteristics,which was implemented using simulation test in FPGA.In this thesis,we retrospectively analyzed and collated the parallel algorithm of FIR filter in the past few years,and explained the FFA algorithm(cascade mode)and fast convolution algorithm(iteration mode)commonly used in parallel structure.The advantages and disadvantages of the parallel FIR filter algorithm are analyzed based on actual requirements and hardware characteristics.Then,the improved structure based on the fast convolution algorithm proposed by other studies is taken as an example.The shortcomings of the improved algorithm are pointed out using simulation calculation: more shifting and addition operations in the pre-matrix structure result in the signal bit widths that may exceed the fixed bit width of the multiplier in the FPGA.The derivation step is more complicated,it is not suitable for high parallelism and introduces errors in fixed point calculation.Aiming at the shortcomings of most structure-level based algorithms,an improvement idea is proposed in this thesis: without changing the parallel structure derived from the existing algorithms,rational allocation of the coefficients between sub-filters reduced the use of multiplier or replace it with other resources to save resources.For example,the 4N+1 order 4 parallel filter in the FFA algorithm structure,the number of sub-filters of symmetric structure is two more than 4N order,which can reduce N multipliers.The coefficients of two sub-filters are reversed in the same way in the sub-filter,it can be realized using one set of dual-port ROM,and one sub-filter is saved in phase-change.Taking the 4-parallel FIR filter with 160-order and 16-bit quantization as an example,the idea proposed in this thesis is used to improve.only one set of dual-port ROM is used,the ROM resource is transformed into a multiplier resource,which saves 76 multipliers(22.4%)than the FFA algorithm.Compared with the improved structure of the fast convolution algorithm,at least 16 multipliers are saved(5.7%,considering only the coefficient bit width,the signal bit width depends on the application environment),and its pre-post structure is simpler and easier to derive,and achieves filtering efficiency above 1 GHz.The parallel structure is applied to the DDC,and the feasibility of the improved method is verified though comparing the resources,operating frequency and filtering results.Finally,in order to verify the FPGA achievability in this thesis,different DSP+ROM collocation schemes were verified in FPGA,and their hardware resources,maximum clock frequency and filtering results were analyzed.Compared with the existing improved structure,the implementation of DSP+ROM not only saves more hardware resources but also has a wider ranger and more flexible of application in practical engineering.