Quantum Effect In Novel Nanometer Field- Effect Transistors And Its Impact To The Performance Of Circuits

Quantum model based on non- equilibrium Green’s function(NEGF) and Poisson equation is adopted to investigate the current characteristics of carbon nano tube field- effect transistors(CNTFETs) and graphene nano ribbon field- effect transistors(GNRFETs) with different gate structures. Furthermore, the research is expended to electrical circuits, and the performance of circuits constructed by CNTFETs and GNRFETs is investigated. Then, the impact of gate tunneling current caused by the reduction of oxide layer thickness to the functionality of circuits is investigated. The main work of this paper can be summarized as follows:Firstly, electrical properties of n- i- n and p- i- n FETs with hetero structure are presented and compared with conventional ones, respectively. Our simulation results illustrate that hetero structure significantly improves on and off state current ratio and sub- threshold swing(SS), and suppresses short- channel effects(SCEs) while delay of FETs is slightly increased.Then, SPICE compatible models for FETs have been built using Verilog- A based look- up table(LUT) in order to present the performance of electrical circuits using HSPICE. The performance parameters of circuits constructed by FETs with hetero structure and conventional one are compared in detail to illustrate the advantage of hetero structure in improving circuits performance. Impact of workfunction of gate materials to the performance of circuits in terms of power, delay and power- delay product(PDP) has been investigated and optimum combinations have been concluded. Furthermore, stability of circuits using p- i- n FETs has been investigated under different gate length, supply voltage and operation temperature. Results illustrate that PDP variation of hetero- dielectric tunneling field- effect transistor(HTFET) is the smallest.Finally, the impact of gate tunneling current to the functionality of logical circuits has been presented. By adding gate tunneling current into SPICE models of FETs, the correctness of functionality of logical circuits is verified. Simulation results illustrate that when thickness reaches 0.5nm, functionality of logical circuits is turned wrong due to the significant increasement of gate tunneling current.