Fabrication Of Ge MOS Devices With La-based High-k Gate Dielectrics And Model Of Gate Direct Tunneling Current

In order to maintain the current drive capability and switching speed of the devices, while scale down the device feature size, the conventional SiO2 gate dielectric was replaced by high-k materials and high mobility channel materials was used to replace the Si substrate. As one of the next generation high-performance MOSFET, high-k gate dielectric/Ge MOS devices have aroused wide interest. However, the ordinary high-k gate dielectric can easily form GeOx interface layer when directly contact with Ge, which causes device performance degradation and prevents the manufacture of high-performance MOSFET. Therefore, it is necessary to find a high-k gate dielectric material which exhibits high-quality interface when directly contact with Ge. Focusing on this issue, the paper studies the fabrication processes and electrical properties of the Ge MOS devices with La-based high-k gate dielectric and the Ge MOS devices with stacked high-k gate dielectric using La2O3 or LaON as passivation layer. As for theory study, a direct tunneling current model is established for the ultra-thin gate dielectric MOS devices.By using parabolic potential well approximation method to obtain the potential distribution and WKB approximation method to solve the quantum effect, a model is established to modeling the direct tunneling current for the ultra-thin gate dielectric MOSFETs. The model is demonstrated by comparing model simulation results with numerical self-consistent results or experimental data. It is found that the model can accurately simulate the gate direct tunneling current for small size MOS devices with different substrates and substrate doping concentration, and different gate dielectric materials and thicknesses.At the aspect of device fabrication, firstly, the Ge MOS devices with La2O3 gate dielectric deposited by e-beam evaporation method are fabricated. And, the effects of five kinds of annealing gases, such as NH3, N2, NO, N2O and O2, on the electrical properties of these devices are analysised and compared. It is found that the best suitable annealing gas for La-based gate dielectric Ge MOS devices is N2. Then, the electrical properties of Ge MOS capacitors with La2O3, LaON, LaTiO or LaTiON as gate dielectric, respectively, are examined, and the optimizing researchs for Ti or N content in LaTiON gate dielectric are carried out. The experimental data demonstrate that, the Ge MOS capacitors with La2O3 or LaON as gate dielectric show good interface quality, but the k value is low, while the LaTiON gate dielectric shows larger k value. Further study found that, when Ti or N content was contronled at an appropriate value, Ge MOS device with LaTiON gate dielectric exhibits ideal interface property and gate leakage current property. In the context of this paper, when the Ti and La2O3 ratio is 14.7%, and Ar and N2 ratio is 24:6, the devices exibit a high dielectric constant (24.6), low interface state density (3.1×1011 eV-1cm-2), and a relatively low gate leakage current density (at Vg= 1V,2.0×10-3 Acm-2).With HfO2 as gate dielectric, the effects of LaON and La2O3 passivation layer on the electrical properties of Ge MOS devices are studied. By comparing electrical properties of the Ge MOS capacitors with HfO2/LaON or HfO2/La2O3 stacked gate dielectric, it is found that LaON passivation layer can effectively block Ge,0, and Hf interdiffusion, while La2O3 passivation layer can not. So, HfO2/LaON gate dielectric Ge MOS devices show better interface property and electrical properties, Such as lower interface state density (4.2×1011 eV-1cm-2), smaller gate leakage current (at Vg=1V,6.1×10-6 Acm-2) and capacitor equivalent thickness (CET,2.0 nm), and nearly neglectable C-V frequency dispersion. Further more, HfTiO/LaON stacked gate dielectric Ge MOS capacitors are fabricated, and good electrical properties and interface property are also obtained.