Analysis And Modeling Of Gate Leakage Current Of MOS Devices With High-k Gate Dielectric

The 45nm CMOS technology has been used in commercial production. In order to avoid the effect of strong gate leakage current caused by the reduction of MOS device deminsions, high-k materials has been generally used to replace conventional SiO2 gate dielectric materials. However, compared with the conventional gate dielectric, high-k materials has kinds of new features, some of which have still puzzled the researchers. Currently,the phenomenon of gate leakage current has become a research hotspot, because it has great impact on the reliability of MOS devices.In this paper, ALD process which is the main deposition method of the high-k gate dielectric is analyzed. The impacts of interface layer on the device characteristics are discussed. On this basis, the theory of gate leakage current in the thin-gate MOS devices is studied. Compared with the formation principle of gate current through the traditional dielectric, the mechanisms of gate current through the high-k gate dielectrics are studied by exprriments and theory analysis. It has been concluded that F-N tunneling and the Schottky emission are the main conduction mechanism in high-k gate dielectric.In addition, the influence of constant voltage stress (CVS) on gate dielectric leakage current is studied. The new argument that gate current depresses after CVS because of the trapping effect is put forward.As the tunneling effect has a great impact on gate leakage current, it is necessary to build a numerical model to analyse its properties. According to the fundamentals of quantum mechanics, the electron density in inversion layer and the tunneling probability are studied by cyclic iterative method in this paper, and the value of gate current is calculated. By analyzing this model, the relationship between gate voltage and leakage current in different conditions has been discussed.