The Reserch And Design Of High-speed Muti-port Shared Aceess Memory

With the development of modern science and technology by leaps and bounds, people become more urgent desire for the high-speed parallel computing, but the mark for the parallel operation is whether can design a high performance in the middle of the module, which used to coordinate among multiprocessing parallel operation. Through the adoption of tight coupling structure design, it can effectively restrict the barrier to address the difficulties. In tight coupling structure, its key part is the multi-port Shared access memory, so the importance of the research and design on it is self-evident.In this paper, though the detailed research and analysis of the design principle of multi port memory of the traditional and the realization, combined with the actual needs of the design, it puts forward a new feasible desigh method of multi port shared memory. The core principle of the new design method is to split the cloning technology and innovation combined with traditional design method, and according to the the principle of time limitation adding a cache unit which can fastly read the last data, thus greatly improving the speed of reading and writing.In this paper, the design of high-speed multiport Shared memory has the function of global writing and reading, very suitable for the parallel operation among multiple processing of data sharing and exchanging. In addition, in the design process in the memory of each write port to join a writing control based on AHB bus arbitritor, to avoid conflict when multiple CPU at the same time to write to the same address, resulting in data errors. The new design structure uses the bottom-up design method, the module design method not only hierarchical is very clear, and flexible in particular, particularly suitable for implementation with the resources of logic unit in FPGA.