The Design And FPGA Implementation Of Muti-port Memory

With the development of science and technology, the demand for high-performanceparallel computing is becoming more and more widely. While the bottleneck of parallelprocessing lies in the design of communication module between the processing units.With the structure of tight-coupling, the factor which restricts the bottleneck can besolved effectively. In this structure, as the core component, the study and design ofmulti-port shared memory shows great significance.Firstly, based on the study of design method and implementation of traditionalmulti-port memory and actual demand, a new method of designing multi-port sharedmemory was introduced in this article, the key of which was a effectively combinationof two traditional method—banking and replication. At the same time, a cache unitwhich can accelerate read out the data last written was added in the structure.The multi-port shared memory presented in this article is a kind of partial write inand overall read out structure. This structure is very suitable for the data exchanging andsharing between multiple processing units. And experiments show that in a certain range,with the increase in depth, the resources of hardware circuit are basically unchanged. Inaddition, the structure has a features of clearly modular and scalability, particularlysuitable for implementation with block memory resources in FPGA.