The Research On Shared Multi-ported Data Cache Architecture Of SCMP

Come the age of huge scale chip, the research on computer architecture faces new tasks: How to use numerous transistors? How to design microprocessor architecture which is suitable to huge scale chip? Nowadays, all of the microprocessor designs are often based on the superscalar technology, which has little room for improving performance more due to its two limitations: hard to realize and low resources utilization. So, the Single Chip Multiprocessor (SCMP) architecture which integrate many simple microprocessors on one chip will soon be an efficient way to increase the performance of microprocessor with the improvements in semiconductor technology.In this paper, we present the Shared Multi-Ported Data Cache Architecture (SMPDCA) on the basis of analyzing the characteristics of the SCMP architecture.SMPDCA architecture has six outstanding excellences: complexity of the control logics of SMPDCA is lower than large scale superscalar; supplying shortest inter-processor communication latency using the shared LI data cache; no cost to maintain cache coherence; hit rate of data cache increase; easy to reuse many softwares of Symmetric Multiprocessor (SMP); exploit the parallelism of applications from many levels.This paper present the architecture model of SMPDCA,and illustrated its function units, and discussed its key techniques, and analyzed the address image policy of multi-ported cache.This paper made performance simulations of SPMDCA in detail using RSIM simulator. This paper present and analyzed four kinds of simulation results: hit rate of data cache, and cost of communications, and affections to the performance due to the long latency of shared data cache, and execution time of applications. Simulation results show that the SMPDCA architecture has better performance than another architecture which data cache is private. Especially SMPDCA architecture has better performance for the parallel applications with many inter-processor communications.There is a key problem in SPMDCA: the hardware cost to realize. To prove the feasibility of SMPDCA, this paper design three architecture for a chip which area is about300 mm2. We got performance simulation results using RSIM. The results of simulationshow that it is really feasible to integrate many simple microprocessors on one chip. And, SMPDCA architecture has better performance than superscalar architecture if their hardware cost is the same.There is another key problem in SPMDCA: the bandwidth of shared data cache. This paper discussed many ways to improve the bandwidth on the basis of analyzing some factors which affect the bandwidth. And described three ways in detail separately: more access ports and non-blocking cache and quick hit buffer(QHB), and analyzed their performance.SMPDCA is a promising processor architecture.