Prototyping Platform Research And Design For Verification Of AVS Video Decoder ASIC

With high-definition digital era arriving, the complexity of video codec algorithm and the scale of video codec chip will increase more and more rapidly. Because of integration of embedded processor and many IP cores, ASIC design cycle will be much longer. In practice, time-consuming verification is common to spend 70-80% of the design cycle, thus become a major bottleneck of VLSI design. In recent years, FPGA application in ASIC verification increases quickly, because in terms of size, physical structure, and speed, the FPGA-based prototyping are very similar to ASIC. Using FPGA to emulate the ASIC has been proved to be the most effective and the most economical way.AVS video decoder is a SoC composed by 32-bit RISC processor, video decoding module, memory, and on-chip bus. Various common FPGA-based prototyping verification platforms have been launched by domestic company or foreign corporation, but they are expensive and structural superfluous, so the paper presents a kind of FPGA-based prototyping verification platform for video decoder chip design. With analysis for the logic resources and memory requirements of AVS video decoder, a single high-end high-capacity FPGA from Altera Corporation was selected to overcome I/O shortages brought by small-capacity multi-chip FPGAs. In accordance with the functions of AVS decoder chip, the platform is divided by several modules using son-mother-board strcture:Motherboard for video I/O interface and daughter board for the FPGA enhanced the anti-interference ability and reduced the design cost. According to design target, the platform can meet the AVS-P2 video standard requirements at 720p@ 60fps format.The paper gave design and debugging process of the platform, and built a minimum system SoC based OpenRISC1200 (OR1200) embedded processor on the platform. Logic synthesizer DC-FPGA was used, which Synopsys company designed for high-end FPGA prototyping, greatly simplified transplantation of the OR1200 IP core from ASIC to FPGA, and accelerated the implementation of AVS video decoding controllor's (OpenRISC1200 processor's) prototyping.With storage resource-rich, reusable and easy upgrade features, the platform paved a smooth way for AVS video decoder ASIC design.