Research And Optimization Of FPGA Packing Algorithm

With the continuous development of FPGA chip, the technology has been applied in various industries. while for the FPGA chip,the software of EDA is widely used, the performance of the tool of EDA requirements are also increasing harsh.So we are committing to research and develop a software of EDA which let the circuit has a high performance.In this paper we aim to improve the performance of packing stage.As one of the most critical step in the software of EDA, packing stage direct impact on the degree of difficulty of placement stage and routing stage,and it has an important impact on the performance of the final circuit,for example, the delay of circuit and the area of circuit.Therefore,improving the performance of packing algorithm is very meaningful to the software of EDA.The paper through research and analysis of existing classical packing algorithm,V_pack,T_V_pack, and refer to the existing thought of packing algorithm, we research and design an efficient packing algorithm which aim to improve the delay of circuit and the area of circuit.The packing algorithm can be divided into two stages: Select Seed stage and Filling CLB.The packing algorithm aim to improve the delay of circuit and the area of circuit,so,it try to reduce the delay of circuit,with the area of circuit unchanged.The paper optimize and improve the two stages of the packing algorithm based on these two indexes.At the Selecting Seed stage, the packing algorithm calculate the critical value and the number of pins of each BLE, to determine which BLE is packed into the new CLB. In the filling of CLB stage, the packing algorithm analyze the relationship between each BLE and the current CLB, so as to calculate the priority of each BLE and fill the current CLB.Compared with the existing algorithms, the algorithm of this paper reduces the time delay of the circuit by 3.3%, and reduces the area of the circuit by 0.12%. It can be seen that the algorithm in this paper has some improvement and optimization in the time delay and area of the circuit.