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The Design And Implementation Of Digital Intermediate Frequency Based On 10 Gbps Wi-Fi

Posted on:2015-01-08Degree:MasterType:Thesis
Country:ChinaCandidate:Y Y LvFull Text:PDF
GTID:2308330473451981Subject:Communication and Information System
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Wi-Fi technology is playing an increasingly important role, for it makes people’s work and life more convenient. Currently, the mainstream Wi-Fi devices work at 2.4 GHz band, which is already very busy. It’s difficult to avoid signal interference when many instruments work at the same time. Besides, with the rapid development of intelligent terminals and their increasingly widespread use, the hundreds of megabits transmission rate can’t meet people’s requirement any more. In this case, the 5th generation Wi-Fi standard-IEEE 802.11 ac emerge.The next generation Wi-Fi standard can enhance wireless data transmission rate and improve signal quality, but the design and test of this wireless products are facing challenges. Thus, we wish to verify the maximum rate that can be transmitted between point and point, basic on 802.11 ac. We use eight antennas to launch or receive signal through three free WLAN band. This thesis mainly research digital IF of Wi-Fi down-link receiver.Firstly, the design of digital IF of Wi-Fi down-link receiver is explored. The detailed design of DDC is given, and the performance simulation for DDC processing is done using Simulink tools. At the end of RF, analog signal is transformed to digital signal through Analog-to-digital Converter. Then after been demodulated, down-sampled and filtered, the signal is transformed to baseband signal.Secondly, a method to implement the design of DDC is given. The implementation of DDC is by building link based on System Generator, and then Verilog code can be generated automatically. A method to improve the real-time of high-data-rate(3840 Msps) digital IF is to process signal through multi-step and poly-phase, then the digital IF can be implemented on FPGA.At last, the functionality and performance of digital IF is verified. The output of DDC is three-way signal, their bandwidth are 160 MHz、160 MHz、80 MHz, the data-rate is all 160 Msps. The output signal can meet the signal spectrum template according to 802.11 ac specification. The 160 MHz signal is composed of two 80 MHz signal, so the output is five-way signal of 80 MHz bandwidth in total.We can get the constellation points after the output five-way signal been demodulated by baseband algorithm, the constellation points coincide with the constellation points of source signal. The SNR of five-way signal are 46.8262 d B, 46.2328 d B, 48.5145 d B, 47.7843 d B, 48.1988 d B; their values of EVM are 0.4557%, 0.4879%, 0.3752%, 0.4081%, 0.3891%. The result of test indicates that the design of digital IF can meet the requirement of functionality and performance.This thesis mainly design and implement the digital IF of next generation Wi-Fi receiver. The method is proved to be feasible. The maximum transmission rate of the system is 10 Gbps. Thus, the study can be used in research of 10 Gbps wireless equipment, which has theoretical significance and practical value.
Keywords/Search Tags:Wi-Fi, Digital Intermediate Frequency, Poly-phase Filter, System Generator
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