Design Of A Digital Down Converter Based On FPGA

Digital down-converter(DDC)implements one of the core technologies of software radio.With the development of digital signal technology,more and more analog circuits used in signal processing have been replaced by Field-Programmable Gate Array(FPGA)with advanced algorithms.The main work of this paper is to combine MATLAB and QUARTUS FPGA to realize the Cascaded integrator-comb(CIC)decimation filter and the two-stage FIR half-band decimation filter.In addition,a numerically controlled os-cillator(NCO)is designed and implemented on the FPGA as a signal source to provide real-time test data and analysis results for the developed decimation filter bankThe main work of this paper is divided into the following five parts(1)Digitally controlled oscillator design,in order to design the digital signal gener-ator of the test decimation filter bank,this paper uses Coordinate Rotation Digital Com-puter(CORDIC)to generate sine and cosine test voltages.Based on the original CORDIC algorithm,an innovative low-delay CORDIC algorithm is designed and verified on the FPGA platform.The hardware resource occupancy rate is much better than that of the traditional CORDIC algorithm.In the case of 16 iterations,Save 7%on hardware re-source consumption.(2)The decimation filter bank design is designed to design a three-stage cascaded CIC decimation filter and a two-stage FIR half-band filter matched with the diaitally con-trolled oscillator.The single-stage filter order is avoided under the requirement of 80dB out-of-band rejection performance.Excessive resource consumption caused by too high(3)Conventional FIR filters require a large number of multipliers and adders,and high-order signal delays are large.In this paper,a parallel pipelined FIR filter structure with constant coefficient multiplication block is implemented on the FPGA platform,and the original adder is saved by the save carry full adder and the save carry half adder,which effectively reduces the hardware of the FIR filter.Occupancy and signal delay time(4)System verification and simulation.This paper combines Matlab and QUAR-TUS to complete the design of the decimation filter bank and digitally controlled oscilla-tor.The performance of the digital downconverter was simulated on the Modelsim platform.Finally,hardware experimental tests are implemented on the same FPGA platform.output signals of the decimation filter bank and the digitally controlled oscillator are extracted by online testing.Finally,the design can achieve the extraction and filtering of the input signal and improve the hardware resource occupancy and delay.(5)The phase value of the digital signal outputted after the digital down converter is detected,and a phase detection method of two-stage CORDIC cascade realized by different iterations of the CORDIC algorithm is proposed.