The Research And Fpga Implementation Of Medium-Frequency Digital Channelized Monitoring Technology

With the development of communication technology, the bandwidth of modern radio monitoring will become wider and wider, and the spectral resolution will become higher and better, so that the monitoring receiver will be forced to have the characteristics of real-time signal processing and wideband access. Although the traditional radio receiver that is used to monitor the signal adopts the structure of software radio and has wider instantaneous bandwidth, because of the limit of the back-end DSP devices and the resolution of receiver is not enough high, so we use the channelized technology that a relatively wide bandwidth signal can be divided into several parallel channels and processed separately, which can effectively resolve the problem between the frequency resolution and real-time processing.On the basis of previous studies, firstly, this paper analyzes the basic theory of channelized receiver techniques, which concludes the band-pass sampling techniques, the frequency conversion techniques and multi-channel receiving techniques. Then designing an efficient structure based on the characteristics of communication signals, which is suitable for real signal digital after AD sampling channelized receiver, furthermore, a detailed theoretical and mathematical verification has been given in this thesis. And the formulation of specific indicators is introduced, such as the way of channel division, extraction ratio, the design of the prototype low-pass filter indexes, etc. At last, the overall structure of the system is given.To prove the validity and feasibility of efficient channel structure’s design in this paper, the software and hardware simulation of this channel structure by using Simulink and System Generator is given. Then the system modeling process and hardware modeling process are introduced. Some main modules are introduced in detail and the simulation results are given.Finally, the receiver structure is implemented by using Verilog hardware design language on FPGA. The realization of each module is introduced in detail by the way of modularization, and the key modules are simulated separately. After the system’s function simulation, and adding the timing constraints and reasonable layout constraints, we prove the design’s validity by using hardware board finally.