The Research And Analysis Of Power Optimization Techniques For Network On Chip Architecture

As a promising solution to the interconnect problem of the wildly used multi-processor architecture, NoC is becoming a hotspot in research. With the growing number of integrated processors and the increasing amount of data exchange, power consumption, an important constraint to NoC designing, is significantly increasing, which leads to a weak battery life in mobile devices and an extra cost to radiators. Therefor a lot of attention is focused on low power architectures and energy saving technologies in NoC system.In this paper, some commonly used power optimization techniques are briefly introduced in the first place. Then the steps to apply CDMA and GALS to NoC are respectively presented in detail.In a CDMA based NoC, data from different senders are transferred on a shared channel to get good performances on throughput and QoS. A traditional CDMA based NoC, which applies complex and logic consuming Walsh coding strategy, suffers from high power consumption. In this paper, a novel one hot code strategy is proposed to the CDMA NoC architecture. With less complexity to realize the coding and decoding process, logic resource is saved. Besides, one hot code stratety suits better, when the scale of NoC expands. Simulations and experiments show that the proposed CDMA NoC achieves better performances on area and power consumption than the traditional Walsh based CDMA NoC.Different tasks and communication requirements are mapped to the integrated processors, leading to different transfer loads to all data links. However, a global clock strategy is applied to the traditional NoC and an equal bandwidth is configured to all data links, which apparently causes an inevitable waste of system resources. In this paper, we proposed a GALS NoC architecture, in which a bandwidth allocation algorithm is used to optimize the bandwidth configuration. Simulations show that under the same circumstance, the proposed GALS NoC gets better utilization of power consumption, compared to the traditional NoC driven by the global clock strategy.