Font Size: a A A

The Reserch Of Thelow Power Critical Technologybased On Circuit Level

Posted on:2011-07-01Degree:MasterType:Thesis
Country:ChinaCandidate:L YangFull Text:PDF
GTID:2178360308953448Subject:Software engineering
Abstract/Summary:PDF Full Text Request
As the development of the deep submicron, the integration level and working frequency of the integrated circuit speed up constantly,and the power consumption becomes the bottleneck of VLSI. Based on the current research status,this paper mainly focuses on the low power technology and its application of the circuit level.Based on SMIC 180nm CMOS library, the characteristics of the subthreshold inverter is researched firstly in this paper, followed by the discussion of the problem in the subthreshold circuit: great influence from the substrate bias voltage as well as the temperature fluctuation. Considering these issues of the subthreshold circuit, this thesis provides a solution to improve its stability, by dynamical modification of the substrate bias voltage setting in the library, and finally realizes the subthreshold inverter design with a dynamic threshold voltage.For the application of ultra-low power consumption, various subthreshold full adders are designed. First, the static adder, transmision function adder and static Energy-Recovery full adder are realized in the subthreshold circuit. Second, based on the previous twelve types of subthreshold full adder research, the whole full adder is divided into three partitions, in which the partition three is suggested by two improvement solution. Then the simulation results indicate that these new adders show lower power consumption.To study the low power technology in high frequency circuit, the PE module applied in the multimedia is taken as the instance. According to its hardware structure, Clustered Voltage Scaling (CVS) is introduced to reduce the consumption by assigning dual power supplies to the circuit. In the work frequency of 50MHz, the power reduction of PE with CVS is up to 34.5% compared to the original one. Additionally, a novel level conversion for less power and delay is presented. Further, the power reduction is improved to 55.3% by refined management of clock gating technology.
Keywords/Search Tags:Subthreshold, TFA, Processor element, Dual VDD Design, CVS, Gating Clock, Level Converter
PDF Full Text Request
Related items