Font Size: a A A

12 Bit Low-noise Bipolar DAC Circuit Design And Physical Implementation

Posted on:2016-02-28Degree:MasterType:Thesis
Country:ChinaCandidate:F YangFull Text:PDF
GTID:2308330470460222Subject:Electronic Science and Technology
Abstract/Summary:PDF Full Text Request
Digital to analog convertor is the important interface connecting between the analog IC and digital IC. It is an indispensable part of the SOC chip. This design of digital to analog convertor(DAC) is used in the MEMS accelerometer. It can provide a stable voltage for the system to eliminating the effects of gravity on accelerometer. This project is supported by the national Twelfth Five Year Plan of major projects. It’s the subproject of MEMS geophones and seismic data acquisition system. The requirements of the system include that the resolution is 12 bit, the margin of source voltage is-5V~+5V, the differential reference voltage is +3.7V and-3.7V, DNL must be less than 0.25 LSB, INL should be less than 2LSB, meanwhile the noise of DAC is required as less than-120dBV?√.The dual-ladder resistor divider structure is used in the DAC. The resistor is divided into 6 bit coarse array and 6 bit fine array in the structure. Compared with the traditional resistor string structure, the dual-ladder resistor structure can reduce the difficulty of the matching and layout. In order to avoid the shortcomings of symmetry and inaccuracy in the reference voltage from traditional voltage reference circuit, the self-adjusted reference structure is presented to producing the voltage of 3.7V and-3.7V. The differential reference voltages circu it reuses the resistors of the DAC as the feedback resistor, which saves a considerable chip area. In order to achieve the purpose of low noise in the systems, this design consider the INL, noise and power consumption and compromise an equal resistance. This paper conducts two taped contrast, and then the noise is optimized after comparing. In addition, due to the resistor equaled to 160Ω and the capacitor equaled to 330μF after the DAC, Class-AB output stage is employed to reduce the setup time and ensure the output is stable in 300 ms.The general flow of analog integrated circuit is used in this design. It has finished all the work of the pre and after simulation in all the corners, layout design, manufacture and test. The DAC has been fabricated in a MXIC 0.5μm CMOS process. The measured results show that the noise of DAC is-120dBV?√ and-140dBV?√ at 3Hz and 15 Hz respectively. And all the results meet the requirements of the system. The DAC has been successfully applied to the MEMS accelerometer.
Keywords/Search Tags:digital to analog convertor, dual-ladder resistor structure, the selfadjusted reference structure, noise, Class-AB output stage
PDF Full Text Request
Related items