Design And Implementation Of Fast Hardware Checkpoint On Embedded System

Currently, the embedded system has been widely used in various areas such as transportation, medical, aerospace and etc. Corresponding reliability issues become the focus of attention. If some emergency occurs in a process of long-running task, the program has to restart, resulting unnecessary waste of resources and time overhead. So, it’s very important to tolerate fault when an emergency happens. Checkpoint technology is such an effective means of fault-tolerance. Computers and embedded systems use this technology to improve reliability.The hardware checkpoint implements on the Cortex-M3core-based embedded system. This checkpoint is used to deal with a sudden power outage. Traditional checkpoint technology is implemented by software. It back-ups the intermediate state every once in a while ensuring that data is not lost. Although it will takes a lot of application resources to set up checkpoint. In contrast, the hardware checkpoint has strong portability and code simplicity. Therefore, the proposed hardware checkpoint has good prospects and significance.First we build an embedded system based on Cortex-M3core. The system includes a soft-core CPU, RAM, UART interface, SPI interface, JTAG debugging interface and external memory. According to the mapping address and interface timing of module, each module is mounted on the AMBA bus for CPU accessing. And the SPI interface bus is configured so that applications can boot from external memory.In term of embedded system based on Cortex-M3core, this paper presents a design for ram checkpoint and a design for register checkpoint. Meanwhile, in order to improve the efficiency of memory checkpoint, a code copy module from external memory to RAM is implemented. The optimization effect is presented by the experimental contrast. A checkpoint demo program is implemented on FPGA platform. The program performs count operation, while the count is sent to LCD screen via UART serial port. When an external interrupt regarded as power outage trigger arrives, the system stores count value in non-volatile ferroelectric memory. After power-on reset, the stored data will be fetched and continue to accumulate. Design of demo system has two purposes. First, it verifies the functionality of each module designed for embedded system; second, it shows the design concept of hardware checkpoint intuitively. In this paper, an embedded system with hardware checkpoint design is established. Meanwhile this paper presents a complete front-end chip design flow, including RTL coding, logic synthesis, timing analysis and power estimation.