VLSI Design Of Arithmetic Encoder In Video Compression System

With the continuous development of information technology,the needs of today’s society for high quality information is Continuously improving. High resolution videos are welcomed by more and more users.However,,in a period of time, for video transmission, the bandwidth is limited. Therefore, how to transfer high-quality video as much as possible in today is a valuable subject in a limited bandwidth. Yet in this subject, the most critical is the highly efficient video compression technology.The H.264 standard is a simple, efficient video compression standard. It is through a variety of complex but effective algorithm to improve the efficiency of video compression.Yet in these algorithms, the entropy coding algorithm,which at the rear end of H.264 encoder, also plays an important role in the improvement of video compression efficiency. There are two entropy coding algorithms in the H.264 standard, CAVLC, which is one of the entropy coding algorithms, introduces the context of elements into the entropy coding, reduces the amount of redundancy and improves the coding efficiency. CABAC based on the basis of arithmetic coding. It is no longer thought to encode a single character, but a long list of code stream is encoded by arithmetic coding ideas. The algorithm greatly improves the coding efficiency for the price of the complexity of the algorithms in exchange for coding efficiency improvement. Currently, the arithmetic coding thought has become the main idea of the future entropy coding algorithm. With the continuous development of the current high rate of FPGA chips, this level of complexity of the algorithm in today’s FPGA platform is possible to meet, so we can handle up to achieve a nuclear CABAC entropy coding in existing FPGA platforms.In this paper, we start from the H.264 standard. First of all, we introduce the entropy encoding video data before passing a few handler: intra prediction or inter prediction, DCT and quantization and so on. Therefore, we focus on the CABAC as the entropy encoding algorithm in the H.264 standard.and we understand the relevant idea of CABAC algorithm by studying the improving ideas range from multiple arithmetic coding to binary arithmetic coding.Therefore,we focuses on the principles and components of CABAC algorithms, and designs appropriate module according to the characteristics of its components.The arithmetic coder designed in this article is dividedinto four parts: a macroblock coding sequence module, a macroblock context management module, a syntax elements binarization module and a binary arithmetic coding module. Among them, the macroblock coding sequence module is carried out in the order of the management of the each current macroblock syntax element enters the encoder. The macroblock context management module records the information related to the surrounding macroblock. The syntax element binarization module is mainly the different syntax elements of H.264 to be binarized.The binary arithmetic coding module is mainly performed to initialize the process to find the probability model corresponding to a syntax element and start the process of the arithmetic coding, while, in the initialization process of binary arithmetic coding, we introduce the pipeline technique to improve system efficiency. After designing the appropriate module, we use modelsim to build a simulation platform for the simulation of each module. Finally, we select XC6VLX365 T FPGA chip in Virtex-6 family from Xilinx company to build a platform, and take the video source 1280x1024 @ 25 f to encode. In this case, themaximum clock of the encoder can be achieved 99.732 MHZ, which is higher than the maximum bit rate of the real-time encoding process,end it can achieve the encoding operation with one clock cycle for a character. Therefore, the encoder can achieve real-time entropy encoding process.of the resolution video.