| One key technique for improving the coding efficiency of H.264, the state-of-the art video compression standard, is the entropy coding technique known as context-adaptive binary arithmetic coder (CABAC). However, the complexity of the encoding process of CABAC is significantly higher than the traditional table driven entropy encoding schemes such as Huffman coding. CABAC is also bit serial and its multi-bit parallelization is extremely difficult. For a high definition video encoder with a 20 Mbps output stream, multi-giga hertz RISC (reduced instruction set computer) processors will be needed to implement the CABAC encoder.; In this work, we investigate and develop an efficient, pipelined VLSI architecture for CABAC encoding. The resulting architecture efficiently decouples and pipelines the critical stages to address the bottlenecks of renormalization, outstanding bits, and regular/bypass coding modes. The final solution is a single cycle throughput for encoding a binary symbol. An FPGA (field-programmable gate array) implementation of the proposed scheme is capable of 97 Mbps encoding rate. An ASIC (application specific integrated circuit) synthesis and simulation for a 0.18 mum process technology indicates that the design is capable of encoding 190 million binary symbols per second using an area of 0.209 mm 2. The proposed design is thoroughly tested for several standard test contents through both software and hardware simulations with test vectors up to a 300 frames foreman content. Also, several designs for CABAC's binarization block and its interface are explored each with different levels of hardware support. |
