The System Design Of Real-time Video Image Acquisition And VGA Display Based On FPGA

Video surveillance is an important part of security and a comprehensive system, which has strong prevention ability. With the rapid development of computer networks and image processing, video surveillance is widely used in military, medical, manufacturing and many other occasions. A real-time video image acquisition and VGA display system based on FPGA was designed in this paper. In the system, the image capture rates is 25 frames per second, and the image display rates is 60 frames per second, and the image pixels are 640 * 480. Meanwhile, a mechanism was proposed for handling the device of different communication rates to optimize the design goals.The real-time video image acquisition and VGA display system was made up of the coding chip configuration module, video capture module, frame buffer control module, format conversion module and image display module. In order to reduce the complexity of hardware system, the i2c-timing was designed by Verilog HDL( hardware description language) based on FPGA, not a dedicated hardware circuit. In addition, the ping-pong operation was combined with state machine method to process the devices of different transmission ratio. This approach not only solved the problem of rate matching, but also reduced complexity of the design. The coding chip configuration module was mainly responsible for initializing the video encoder chip. The video capture module was used for extracting valid video signal. The frame buffer control module could store the image data. The signal format was converted by the format conversion module. The image display module was used for displaying the video image. In the frame buffer control module, a mechanism was proposed for handling the device of different communication rates. By using this mechanism, the device of slower acquisition rate could meet the transmission requirement of the faster display device, and this mechanism not only simplifies the design task, but also optimizes the results.Finally, the simulations of test-case, synthesis and code coverage were made. The simulation results showed that the functions and timing of the system is designed properly. The synthesis results showed that the resources ratio of FPGA is only used 9%,and the maximum speed of the system is up to 100 MHz, and the code coverage is up to 95%. From the results above, the function of image acquisition and display could be achieved and meet the design goals.