High Definition Video Acquisition And Display System Based On FPGA

With the development of society and innovation in the field of science and technology,it has brought rapid development to all walks of life.The security industry has also demonstrated more and more important influences and functions,especially the urban peace,strong science and technology,and campus security.The promotion and application of government's municipal construction,security products based on high-definition video surveillance show the momentum of large-scale,ultra-normal development.In the past,the field of video surveillance was mainly analog and analog mixed monitoring equipment.Today,traditional monitoring equipment has been gradually replaced,and replaced by digital,intelligent high-definition digital monitoring equipment.The traditional resolution is mainly CIF,D1 format,these traditional image resolution formats are gradually being replaced by all-digital high-definition resolution standards.Million HD video is rapidly occupying all fields and being accepted by people.Video surveillance has become a very important part of security systems in all areas.Thesis is based on FPGA-based high-definition video capture and display system.It aims at the continuous advancement of high-definition digital video technology in recent years and has been in schools,national security,environmental protection industries,coal mining,military,armed police,steel industry,forestry,transportation,commerce,medical and other fields.After extensive application,the market is in urgent need of relatively low cost,small size,and reliable performance of high-definition video capture and display systems.It has developed a practical high-definition video capture and display system based on its FPGA technology.The system focuses on the research direction at home and abroad.It mainly researches on the basis of FPGA(Field Programmable Gate Array)as the core,adopts high-definition camera(resolving power of 1080P)to collect image information in real time,and sends high-definition image data stream to FPGA.The process is then sent to the HD monitor for display.According to the characteristics of FPGA,powerful parallel processing capability and field programmable features,the algorithm can be more easily implemented,making the system have better inheritance and portability.The system mainly realizes the collection,processing and display of high-definition video information.When a long-distance transmission is needed,only a few changes can be made to adapt to the back-end data transmission and high-definition display.The research work of the thesis is mainly reflected in the following aspects:First,the status quo and the latest achievements of high-definition video capture and display technology at home and abroad are studied,and a design scheme of an application system that uses FPGA to capture,process,transmit,and display high-definition video signals is proposed.Secondly,the design of each functional unit of the system is performed,including a front-end high-definition video acquisition module,a Camera Link interface differential single-ended signal module,a central data processing module,a storage buffer module,a DVI timing generation module,and a back-end high-definition display module.The HD camera captures an image resolution of 1920x1080,a frame rate of 25 fps,an image decoding chip DS90CF386,and an image encoding chip TFP410.Third,the hardware and software modules of the system are all autonomously designed.One of the advantages of designing with the FPGA architecture compared to the traditional monitoring equipment is that it can minimize the processing delay of the entire system and adjust the DDR3 memory if necessary.Caching the data can reduce the delay to 1 frame.Another advantage is that with the help of FPGA's rich pins and powerful parallel processing capabilities,multiple video information can be acquired and processed at the same time,which reduces the cost and improves the data processing speed.Fourth,the system uses ISE14.7 software platform for programming and online debugging,using Verilog hardware description language for code writing.During the pre-simulation and debugging,the timing simulation and functional simulation are performed by generating black and white grayscale bars and colorful block mini data instead of the Camera Link interface data input within the program.After each module is confirmed normal,the image data is switched from the analog source.For debugging of real images,the system uses a professional third-party EDA simulation tool Modelsim to perform waveform simulation on each module.After the timing simulation reaches the desired design target,the program is downloaded to the FPGA chip for debugging,and it is verified whether the video information output by the FPGA to the display is consistent with the information input by the camera.When the image is switched to the real image,the image quality is seriously distorted.A detailed analysis and debugging are performed for this situation.Finally,the problem is solved and the problem is solved by the step-by-step debugging scheme.The system achieves a predetermined design effect.