Design And Implementation Of Pulse Compression And The Key IP Core

Radar plays a leading role in many fields for modern military and civilian use, so the radar signal processing is significant. With the development of radar signal processing and the very large scale integrated circuit, in order to adapt to the complex environment and a variety of work modes, data in radar signal processing are not simply the fixed point data, floating point data are widely used in order to be able to handle a greater dynamic range and improve the precision. But the hardware consumption of the floating point system is too large. To balance the dynamic range and hardware consumption, block floating point data is used as a better method.In radar signal processing, pulse compression balances the radar transmitting power and the range resolution, which is widely used. In this paper, the hardware implementation of pulse compression is studied.In this paper, the block floating point processor of the pulse compression is designed and implemented, as well as the key Fast Fourier Transform(FFT) and its inverse transform(IFFT) in radar signal processing. Firstly, the principles of pluse compression, FFT/IFFT and the block floating point data are introduced. Secondly, combining with the principle of hardware implementation of FFT/IFFT, a block floating point FFT/IFFT processor is designed, in which the points are configurable and the inout data type can be either fixed or floating. With the emphasis on the hardware consumption, the storage method is optimized and a frequency doubling clock is used in the internal computation and storage, thus the storage memorys and the computation units can be reused, which can achieve the more utilization of the hardware. The block floating point pulse compression(PC) processor with the configurable inout data type and data length is planned using the designed FFT/IFFT. A four-channel method is researched in the PC processor to reduce the latency of the processing. Finally, the block floating point PC processor is implementated in RTL with all the research methods above.In this paper the function verification of the four-channel block floating point pulse compression processor is performed in Matlab and Modelsim environments. The relative error of the FFT/IFFT is analyzed, and the result is in orders of 10-6. The signal-to-noise ratio is about at 200 d B. The latency of the four-channel PC is reduced,and the FPGA validation is made. The proposed design is synthesized in SMIC 0.13μm technology library using Design Compiler®. The internal frequency could reach at 200 MHz, and the main frequency is at 100 MHz. The formal verification and the static timing analysis for the netlist are performed.