Hardware Design And Implementation Of Floating-point Instruction Based On AltiVec

In order to improve multimedia processing capabilites of embedded devices, manufacturers have added SIMD coprocessor instruction subset on its main processor, AltiVec is the PowerPC SIMD coprocessor instruction subset, used to enhance data-level parallelism. Compared to traditional PC devices, embedded devices have more restrictions on area and power. Therefore how to compromise in terms of speed, area, power became the focus of AltiVec design. Vector Floating Point Unit is the most important instruction subset, whose performance area and power consumption will affect AltiVec.In this paper, Vector Floating Point Unit hardware has four cycles and is fully pipelined, with MAF as the core datapath. MAF is divided into four stages: multiplication, addition, normalization and rounding stage. Most of the other instructions will reuse the MAF datapath. In terms of area and power consumption, two hardware-reuse strategies are used to reduce the overall area. On the verification of functional units, using SystemVerilog verification to verify every instruction of the functional unit.Finally, synthesized in SMIC 0.13 um process, using DesignCompiler, proposed design can achieve 24% area reduction with only 3% speed degradation.In the design of the top-level path, AltiVec receives instructions from the PowerPC APU interface. Decodeing to generate CS signal,and to detect instruction dependency and bypass control. One cycle operand read and several cycles to execute, one write-back cycle. Alti Vec has a separate vector register file, which has 32 128-bit vector registers, three read ports to ensure that the three vectors can be read simultaneously operands, five write ports to ensure that five vector results can be writen back at the same time.