Research And Realization Of The 128-bit Floating-Point Multiply-Add Fused Unit

The floating-point multiply-add fused (MAF) operation treats the multiplication and the addition as an inseparable operation. There is no need to round the internal results, and the precision of the result and FLOP are improved. High-performance floating-point multiply fusion research, which has independent intellectual property, is significance for improving performance.This thesis researches the architecture of MAF unit and the method to design high-performance MAF unit. It present a design of 128 bits floating-point multiply-add unit. The thesis's main work and achievements include:1.Propose a 128-bit floating-point multiply integration architecture. A five-point structure of the pipeline ; Using block-multiplication and addition, reducing the length of the critical path, the increased computing speed; Summation of the plot for the adoption of improved 4:2 CSA Carry Save Adder tree structure, CSA tree structure to reduce the logic series.2.Designed and implemented 128 of the three input leading-one prediction architecture. Comparison of two input DT leading-one-prediction and three input leading-one-prediction algorithm for the exploration architecture provides a theoretical basis; using modular priority coding tree and realized the three leading-one-prediction input architecture, the three input leading-one-prediction reduce by 31% area than traditional DT leading-one-prediction, and critical path delay reduced 26%.3.Proposed 128 floating-point multiply-add fused Test Set Generation. According to the IEEE-754\854 standards, in accordance with the terms of the data will encourage the importation of test data for the nine equivalence of categories, targeted to produce artificial selection and random data input incentive to reduce test vectors, while maintaining high test coverage. Based on the test set and achieved 128 floating-point increase integration by parts of simulation and FPGA logic simulation.This design of 128 bits floating-point fused unit implemented with verilog language at RTL-class. The synthesis result shows that design can work at about 202MHz, critical path delay 4.93us, 119,000 and-non-doors, on a smic0.13-mirco process.