Analysis And Design Of High-performance Floating-Point Unit

Floating-Point Unit is a special microprocessor circuitry unit that deals with floating-point arithmetic operations, which is widely used in Scientific Arithmetic,CPU,DSP(digital signal processing)and Image Processing.In this paper we mainly study for the key technology of floating point arithmetic. First, in this paper we study the mainly technology of floating point arithmetic. In this part we give the principle of two data paths adder and three data paths adder, and the structure of super precision floating point adder. In the super precision floating point addition, significant digits addition become more important for the reason of the significant digits went up. In order to deal with the significant digits addition we designed three inputs adder tree, and give a simple performance discuss of this method. Second, High-radix booth is of great importance for speeding up multiply by reducing the number of partial products. But it also adds great burdens on the adder of the multiplier on timing and area. On the basis of analyzing the theory of digital multiply and the principium of partial products shrinking, a radix-x booth algorithm is proposed. It can achieve speeding up multiplying dynamically without burdening the adder. A 32-bit mantissa floating point multiplier based on this algorithm is also introduced. It is better than a 32-bit mantissa radix-8 floating point multiplier in both area and timing. For the last part we sum up our work, and give the main succulent work.