Design Of Double Precision Floating Point Unit

The floating-point number can express a wide range with high precision, and is able tomeet the requirements of information accuracy in modern society. However, the floating-pointoperation is not only complicated but also time-consuming, so FPU occupies the key part ofmodern processors. MAF performs multiply-add operation with a single instruction, insteadof the traditional first multiplication then addition, this operation reduces an intermediaterounding, improves the accuracy of results, and decreases the delay. At the same time, MAFcan perform addition, subtraction and multiplication, so it has been widely used in modernprocessors.After analyze and compare the traditional and low-latency floating-point multiply-addfused structures, the low-latency structure is selected as the design template. The design isdivided into three pipelines, and some improvements are made in order to support theoperations of denormalized numbers. The first stage performs the multiplication of mantissasand the alignment shift. The second stage makes preparations for the normalization shift inadvance, including leading-zero anticipation and result sign detection. The third stageperforms the normalization shift, addition and rounding.For further optimizing, three key modules have been improved. The alignment shift modulehas been improved in order to avoid bidirectional shift, while the shift and the formation ofshift amount perform in parallel. The leading-zero anticipation module has been improvedwith the proposed three-input algorithm and the priority coding tree based on the4:2priorityencoder. In the second stage, adopt the dual-channel half adder instead of the ordinary adder,so as to avoid the full-length complement before leading-zero anticipation normalization shift,perform a part of normalization shift in advance, and fill the delay gap of leading-zeroanticipation module.Finally implement the simulation and synthesis of the design. The directly generated testvectors have been used for verification, results show that the desired multiply-add functioncan be achieved. Implement the synthesis in the SMIC0.13um process conditions, resultsshow that the improved alignment shift module offers14.4%sa vings in delay while the areais basically unchanged, the improved leading-zero anticipation module offers17.3%savings in delay and21.5%savings in area. The delay of the designed floating-point multiply-addfused unit is8.6ns, and the area is approximately equal to the area of89,000NAND gates.