The System Design Of Block Floating Point FFT Processor

With the rapid development of integrated circuit technology, the technology of EDA has been becoming an important design method. And this technology has already used in many fields, especially in digital signal process field. Moreover, the gates counts and system complexities have an exponential increase, and the functional verification of product plays a significant role. Field Programmable Gate Array (FPGA) is a semicustom integrated circuit and a new type of programmable device. With the wide application and improvement of FPGA, the method of electronic system design is innovated all the time.Discrete Fourier Transform (DFT) is the important transformation tool of digital signal analysis and processing systems. And Fast Fourier Transform (FFT), the fast arithmetic of DFT, is the vital technique of DSP. FFT has already widely applied in speech recognition, image processing, radar system, spectrum analysis, and so on. Different systems need different performance FFT. And with the advent of next generation 4G based on FFT, studying the implementation of FFT processor is necessary. So this paper proposes an FFT processor design base on FPGA.This paper introduces the basic theory of FFT. And the hardware architecture and principle of 64 point FFT are researched according to the arithmetic property of FFT. In particular, it discusses that using which method to carry out FFT, DIT or DIF, radix 2 or radix 4. Moreover, the advantages and disadvantages of floating point, fixed point and block floating point are compared, so it finally uses 16 bit block floating point to design the FFT system. The whole design adopts synchronous sequential architecture, serial input and output and parallel computation in FPGA. Considering the property of twiddle factors and ping-pong RAM, a new simple address mapping is proposed and the clock cycles is reduced.This paper realizes a block floating point FFT system of 64 points by using hardware description language at the software platform of QuartuslI 8.0, ModelSim-Altera 6.1g and ModelSim 6.2b and at the hardware platform of Altera CycloneII EP2C35F484C8. And the function simulation and time simulation of the system are passed. The experiment simulation indicates that the accuracy of calculation result is rather good, and the speed of the system can meet the requirment of common realtime digital signal processing.