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A Study On ATE And Bench Test Cost Reduction

Posted on:2014-07-14Degree:MasterType:Thesis
Country:ChinaCandidate:T T DongFull Text:PDF
GTID:2308330464957826Subject:Integrated circuit engineering
Abstract/Summary:PDF Full Text Request
With the development of IC fabrication techniques, the speed inside chip and their I/O become much faster, which makes ATE configurations become one of the key limitations during test. Also the integrity of the chip increase greatly which makes the test time increase several times over. We have to increase our test coverage of the chip to make sure its quality. But from another point of view, we cannot increase our test time too much since we have to control the production cost. That’s why production cost reduction without any loose of the test coverage become more and more important.In this paper, we introduce some cost reduction optimization method starting from IC design, include ATE and bench test. All those methods will not impact test coverage and approved its effectiveness during production.Frist, considering production test cost at the very beginning of the chip design. We analysis test hardware cost, test time, test repeatability and stability, and also the test coverage of failure chip from last generation. We introduce test method optimization of PLL jitter which reduces test time from IS to 3mS and reduce 17% DPM. And include some comparison of different test method, like high speed interface test and so on. Also point out the shortage of the test coverage of some current test method. The paper also introduces how to run mbist diagnosis on the bench board to reduce ATE engineer investigation test time.Second, we introduced full test flow and how to simplify them during chip testing. We analysis the important component parts of the test cost, introduce the method to reduce test cost from hardware configuration, included optimization of test program, simplification of test pattern, the improvement of test yield and reduction of chip retest rate.Then, the paper introduced how to optimize test hardware and reduce test time during bench test. At last to achieve the reduction of overall test cost, we can remove some redundant test items from ATE or bench test; or move some long test time items from ATE to bench.
Keywords/Search Tags:test cost, test time, ATE, bench test, PLL jitter, DPM
PDF Full Text Request
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