Research And Implementation Of SoC/IP Test-Bench

IP reused technology speeds up SoC development progress and brings greater challenge to functional verification of SoC/IP. How to improve quality and efficiency is a practical problem that needs to be resolved when developing SoC/IP. Under the background of verifying the SoC chip designed, verification characteristics and requirements are investigated. Aiming at high quality and high efficiency, this thesis focuses on the research of test-bench structure, design and implementation combining with dynamic simulation technology and test-bench design technology.Layered function verification approach for the process of verification is proposed and layered verification scheme is established. Five important aspects are optimized, including test-bench structure and implementation, stimulus generation, files management, verification steps and so on. Layered bus-based test-bench structure with the property of perpendicular and horizontal modularization partition is designed. The main modules, such as transaction test scenarios and reusable components are accomplished.NandFlash Controller (NFC) is designed in the thesis in order to control NandFlash by CPU flexibly. Based on the analysis of functional characteristics and protocol specification, NFC oriented Coverage models and assertions are set up by covergroup and SystemVerilog Assertions (SVA) respectively. Coverage driven verification and assertion based verification are used together in the proposed test-bench.The SoC/IP test-bench is built using SystemVerilog language with Object Oriented Programming (OOP) and verification environment is established with layered file management in the last section. Automatic verification process is executed with scripts, and the results are analyzed.Experiment results show that above-mentioned layered and bus-based test-bench supports module reuse and can progress the functional verification of SoC/IP with high flexibility and efficiency.