Design And Verification Of DCM In The FPGA Based On SOI Process

FPGA is a kind of semiconductor product which develops from SPLD, CPLD, EPLD programmable device. At present, the usage of FPGA has been extended from telecommunication to various military and civil fields, such as controller, navigation, and aerospace. As a programmable ASIC, not only FPGA overcomes many shortages of custom design IC but also figure out the limitation on number of earlier generations’ gates. FPGA is one of the foundations of digital system design.Digital Clock Manager is an important part of FPGA chips. DCMs manage clocks of FPGA system. Clock skew and clock jitter are the main problems in digital system. Whether the DCMs can work properly or not directly affects functionality and performance of FPGA, especially in high-rate system. Clock Manager is based on phase locked loops or delay locked loops, now. DCMs of FPGA include DLLs and clock distribution network.This paper presents a DCM with all-digital DLLs and clock distribution network. The DCM can be divided into several different logical blocks, lock circuit, phase shift circuit, output circuit and clock distribution network. Lock circuit is the main circuit of thesystem; phase shift circuit is the subordinate circuit. Both main circuit and sub_circuit consist of phase detector, control circuits and delay circuits. When it works, main circuit and sub_circuit have different responsibilities. Sub_circuit accomplishes phase shift through delay circuits to generate clocks with the phase of 90°,180°,270°,360°.Main circuit achieves the synchronization between clk_in and the closest clock generated from sub_circuit. Beside providing clocks with the phase of 90°,180°,270°,360°, output circuit also generates many kinds of divided clock signals and multiple frequency clock signals.