SDH Equipment Clock Design And Realization Based FPGA

SDH Equipment Clock(SEC) is the important part of SDH Optical transport device. It's the base of synchronous network which are maked of SDH devices, and it's the basic device which ensures SDH device works reliability. The core part of SEC is maked up of Phase Locked Loops. The structure and design principle of SEC are presented in this paper, the SEC is designed with All Digital PLL(ADPLL) based FPGA.The SEC can export a system clock T0 and two external clocks which can choose referenced clock independently. The system clock supports three working mode of Free-run,Holdover and Locked. In Free-run mode, the system clock is locked local high-steady Oscillator. In Locked mode, the SEC can locked one of all input referenced clock. The system clock is steady when source is changed. After all referenced clock are loss, the SEC will work in Holdover mode, But in Holdover mode, the system clock is high-steady also. Whatever working mode, the system clock of the SEC can comply with all clock specification which regulated in ITU-T G.813 recommendation. The external output clock can locked one of the all input line referenced clocks.Because it's designed with FPGA, it can achieve cheaply and easily. Test results indicated that the SEC is fully comply with all clock specification which regulated in ITU-T G.813 recommendation.