Research And Design Of BiCMOS Distributed Step Attenuator

With the rapid development of wireless communication technology and semiconductor process, Si Ge Bi CMOS process enables low-cost, high-density microwave monolithic circuit possible. As the amplitude control circuits, variable gain amplifier and attenuator are widely used in the phased array system. In particular, VGA does not have high linearity and low power consumption, which makes digital attenuator more widely used in phased array system.This paper is designed in Jazz 0.18μm Si Ge Bi CMOS process, and study a 10~20GHz5-bit distributed step attenuator. The circuit design methods are as follows: five basicattenuation structure are designed and well optimized, where the basic attenuationmodules consists of switch attenuator and distributed step attenuator; then the overalldistributed attenuator is achieved by cascading the five basic attenuation modules and isoptimized. Some research results are achieved in this design:Firstly, on-chip microstrip line process is implemented. Based on Jazz 0.18μm Si Ge Bi CMOS process, it is designed by using metal6 as a signal layer and metal1 as a ground plane, and the microstrip line characteristics are verified by Sonnet electromagnetic simulation software.Secondly, the overall attenuation flatness characteristics of distributed attenuator are improved. The attenuation flatness improvements are mainly from two aspects:(1) the basic attenuation modules. In the switch attenuator, NMOS switch high-frequency switching characteristics are studied to decrease attenuation fluctuations through the gate series resistance, Deep N-well structure and body floating technique, and the attenutaion of the switch attenuator decreases with increasing frequency; in the distributed step attenuator, the research of flatness focuses on the influence of the electrical length. When the electrical length is 11.25°, the fluctuation of the attenuation curve is small, and the attenuation of the distributed attenuator increases with increasing frequency.(2) the overall distributed attenuator. The trends of the attenuation responses of the switch attenuator are opposite to the distributed attenuator with increasing frequency, then the overall attenuator is designed by cascading the two basic attenuators to improve the attenuation flatness.Thirdly, a smaller relative phase is achieved, and its means the lower phase errors between the reference state and the attenuation state. Stable phase change is also a requirement of the attenuator, then this requirement is realized by introducing a inductive low-pass filter network into the switch attenuator.Fourth, this paper achieves a lower insertion loss while taking into account the small chip area. The lower insertion loss is obtained by the basic distributed attenu ator module, and a large chip area is occupied at the same time; However, The larger insertion loss is obtained by the basic switch attenuator module, and a small chip area is occupied at the same time; Therefore, the smaller attenuation modules are realized by the switch attenuator modules, and the bigger attenuation modules are implemented by the distributed attenuator modules, then the design is able to have lower insertion loss and smaller chip area.Finally, in the operation bandwidth 10~20GHz, the simulation results show that the attenuator has 31 d B dynamic range stepped by 1d B, attenuation flatness is less than 0.5d B, the insertion loss is 5.08~6.9d B, relative phase is 1°~16°, the input return loss is more than 11 d B, the output return loss is more than 12 d B, the input 1d B compression point is 15.19 d Bm at 15 GHz, and the core chip area is 1.8×1.0mm2(not including Pad area). All these performances are able to meet the design requirements.