| With RFID technology's large-scale applications in many social areas, It has been a significant impact on improving people's quality of life, enhancing the economic efficiency of enterprises, strengthening public safety and raising the level of information-based society. RFID is a new non-contact automatic identification technology for the object identification. Since RFID technology has been put out, it has been extremely rapidly developped both in theory and in practice. But the research on single chip RFID reader achieves relatively Less. This thesis concentrates on the digital baseband of single-chip RFID readers.In this thesis, on the basis of the UHF RFID reader digital baseband system architecture, algorithms and their relative technologies developed in these fields, we realize the system and module design of the key technology of the RFID reader digital baseband based on EPC C1G2 protocols.These works are presented in this thesis:1.Detailed analyze on the EPC Global Class 1 Generation2 protocol, including physical layer, tag-identification layer, tag memory, tag state and the communication process between the reader and tags.2.Put out the framework structure of the digital baseband system on the basis of the EPC Global C1G2 protocols, and analyze on the principles and design methods of several critital modules. The erlcode/decode methods, data rates, modulation, check methods and parameters such as collision arbitration mechanism are confirmed.3.The critical modules of the digital baseband system has been designed, including PIE encoding, raise-cosine filter, Hilbert filter, CRC5\16 check, FIR and HR channel filter, sampling circuit, FM0 decoding, collision detection, the control unit and so on. The structure of raise-cosine filter, Hilbert filter and IIR channel filter is optimized.4. Some modules have been implemented on target device: Xilinx Virtex4 series FPGA: xc4vlx160 and has been implemented in xc4vlx160 device successfully. |
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